`default_nettype none
module Accelerator_top_wrapper #(
  /* for offset read */
  parameter integer C_M00_AXI_ADDR_WIDTH = 64 ,
  parameter integer C_M00_AXI_DATA_WIDTH = 512,
  parameter integer C_M01_AXI_ADDR_WIDTH = 64 ,
  parameter integer C_M01_AXI_DATA_WIDTH = 512,
  /* for offset read */
  /* for info read */
  parameter integer C_M02_AXI_ADDR_WIDTH = 64,
  parameter integer C_M02_AXI_DATA_WIDTH = 512,
  parameter integer C_M03_AXI_ADDR_WIDTH = 64,
  parameter integer C_M03_AXI_DATA_WIDTH = 512,
  /* for info read */
  /* for vertex data write */
  parameter integer C_M04_AXI_ADDR_WIDTH = 64,
  parameter integer C_M04_AXI_DATA_WIDTH = 128,
  /* for vertex data write */
  /* for vertex id information */
  parameter integer C_M05_AXI_ADDR_WIDTH = 64,
  parameter integer C_M05_AXI_DATA_WIDTH = 128,
  parameter integer C_M06_AXI_ADDR_WIDTH = 64,
  parameter integer C_M06_AXI_DATA_WIDTH = 128,
  parameter integer C_M07_AXI_ADDR_WIDTH = 64,
  parameter integer C_M07_AXI_DATA_WIDTH = 128,
  parameter integer C_M08_AXI_ADDR_WIDTH = 64,
  parameter integer C_M08_AXI_DATA_WIDTH = 128,
  /* for vertex id information */
  /* for cycle */
  parameter integer C_M09_AXI_ADDR_WIDTH = 64,
  parameter integer C_M09_AXI_DATA_WIDTH = 32,
  // for degree
  parameter integer C_M10_AXI_ADDR_WIDTH = 64,
  parameter integer C_M10_AXI_DATA_WIDTH = 512,
  parameter integer C_M11_AXI_ADDR_WIDTH = 64,
  parameter integer C_M11_AXI_DATA_WIDTH = 512 
)
(
  // System Signals
  input  wire                              ap_clk         ,
  input  wire                              ap_rst_n       ,
  // AXI4 master interface m00_axi
  output wire                              m00_axi_awvalid,
  input  wire                              m00_axi_awready,
  output wire [C_M00_AXI_ADDR_WIDTH-1:0]   m00_axi_awaddr ,
  output wire [8-1:0]                      m00_axi_awlen  ,
  output wire                              m00_axi_wvalid ,
  input  wire                              m00_axi_wready ,
  output wire [C_M00_AXI_DATA_WIDTH-1:0]   m00_axi_wdata  ,
  output wire [C_M00_AXI_DATA_WIDTH/8-1:0] m00_axi_wstrb  ,
  output wire                              m00_axi_wlast  ,
  input  wire                              m00_axi_bvalid ,
  output wire                              m00_axi_bready ,
  output wire                              m00_axi_arvalid,
  input  wire                              m00_axi_arready,
  output wire [C_M00_AXI_ADDR_WIDTH-1:0]   m00_axi_araddr ,
  output wire [8-1:0]                      m00_axi_arlen  ,
  input  wire                              m00_axi_rvalid ,
  output wire                              m00_axi_rready ,
  input  wire [C_M00_AXI_DATA_WIDTH-1:0]   m00_axi_rdata  ,
  input  wire                              m00_axi_rlast  ,
  // AXI4 master interface m01_axi
  output wire                              m01_axi_awvalid,
  input  wire                              m01_axi_awready,
  output wire [C_M01_AXI_ADDR_WIDTH-1:0]   m01_axi_awaddr ,
  output wire [8-1:0]                      m01_axi_awlen  ,
  output wire                              m01_axi_wvalid ,
  input  wire                              m01_axi_wready ,
  output wire [C_M01_AXI_DATA_WIDTH-1:0]   m01_axi_wdata  ,
  output wire [C_M01_AXI_DATA_WIDTH/8-1:0] m01_axi_wstrb  ,
  output wire                              m01_axi_wlast  ,
  input  wire                              m01_axi_bvalid ,
  output wire                              m01_axi_bready ,
  output wire                              m01_axi_arvalid,
  input  wire                              m01_axi_arready,
  output wire [C_M01_AXI_ADDR_WIDTH-1:0]   m01_axi_araddr ,
  output wire [8-1:0]                      m01_axi_arlen  ,
  input  wire                              m01_axi_rvalid ,
  output wire                              m01_axi_rready ,
  input  wire [C_M01_AXI_DATA_WIDTH-1:0]   m01_axi_rdata  ,
  input  wire                              m01_axi_rlast  ,
  // AXI4 master interface m02_axi
  output wire                              m02_axi_awvalid,
  input  wire                              m02_axi_awready,
  output wire [C_M02_AXI_ADDR_WIDTH-1:0]   m02_axi_awaddr ,
  output wire [8-1:0]                      m02_axi_awlen  ,
  output wire                              m02_axi_wvalid ,
  input  wire                              m02_axi_wready ,
  output wire [C_M02_AXI_DATA_WIDTH-1:0]   m02_axi_wdata  ,
  output wire [C_M02_AXI_DATA_WIDTH/8-1:0] m02_axi_wstrb  ,
  output wire                              m02_axi_wlast  ,
  input  wire                              m02_axi_bvalid ,
  output wire                              m02_axi_bready ,
  output wire                              m02_axi_arvalid,
  input  wire                              m02_axi_arready,
  output wire [C_M02_AXI_ADDR_WIDTH-1:0]   m02_axi_araddr ,
  output wire [8-1:0]                      m02_axi_arlen  ,
  input  wire                              m02_axi_rvalid ,
  output wire                              m02_axi_rready ,
  input  wire [C_M02_AXI_DATA_WIDTH-1:0]   m02_axi_rdata  ,
  input  wire                              m02_axi_rlast  ,
  // AXI4 master interface m03_axi
  output wire                              m03_axi_awvalid,
  input  wire                              m03_axi_awready,
  output wire [C_M03_AXI_ADDR_WIDTH-1:0]   m03_axi_awaddr ,
  output wire [8-1:0]                      m03_axi_awlen  ,
  output wire                              m03_axi_wvalid ,
  input  wire                              m03_axi_wready ,
  output wire [C_M03_AXI_DATA_WIDTH-1:0]   m03_axi_wdata  ,
  output wire [C_M03_AXI_DATA_WIDTH/8-1:0] m03_axi_wstrb  ,
  output wire                              m03_axi_wlast  ,
  input  wire                              m03_axi_bvalid ,
  output wire                              m03_axi_bready ,
  output wire                              m03_axi_arvalid,
  input  wire                              m03_axi_arready,
  output wire [C_M03_AXI_ADDR_WIDTH-1:0]   m03_axi_araddr ,
  output wire [8-1:0]                      m03_axi_arlen  ,
  input  wire                              m03_axi_rvalid ,
  output wire                              m03_axi_rready ,
  input  wire [C_M03_AXI_DATA_WIDTH-1:0]   m03_axi_rdata  ,
  input  wire                              m03_axi_rlast  ,
  // AXI4 master interface m04_axi
  output wire                              m04_axi_awvalid,
  input  wire                              m04_axi_awready,
  output wire [C_M04_AXI_ADDR_WIDTH-1:0]   m04_axi_awaddr ,
  output wire [8-1:0]                      m04_axi_awlen  ,
  output wire                              m04_axi_wvalid ,
  input  wire                              m04_axi_wready ,
  output wire [C_M04_AXI_DATA_WIDTH-1:0]   m04_axi_wdata  ,
  output wire [C_M04_AXI_DATA_WIDTH/8-1:0] m04_axi_wstrb  ,
  output wire                              m04_axi_wlast  ,
  input  wire                              m04_axi_bvalid ,
  output wire                              m04_axi_bready ,
  output wire                              m04_axi_arvalid,
  input  wire                              m04_axi_arready,
  output wire [C_M04_AXI_ADDR_WIDTH-1:0]   m04_axi_araddr ,
  output wire [8-1:0]                      m04_axi_arlen  ,
  input  wire                              m04_axi_rvalid ,
  output wire                              m04_axi_rready ,
  input  wire [C_M04_AXI_DATA_WIDTH-1:0]   m04_axi_rdata  ,
  input  wire                              m04_axi_rlast  ,
  // AXI4 master interface m05_axi
  output wire                              m05_axi_awvalid,
  input  wire                              m05_axi_awready,
  output wire [C_M05_AXI_ADDR_WIDTH-1:0]   m05_axi_awaddr ,
  output wire [8-1:0]                      m05_axi_awlen  ,
  output wire                              m05_axi_wvalid ,
  input  wire                              m05_axi_wready ,
  output wire [C_M05_AXI_DATA_WIDTH-1:0]   m05_axi_wdata  ,
  output wire [C_M05_AXI_DATA_WIDTH/8-1:0] m05_axi_wstrb  ,
  output wire                              m05_axi_wlast  ,
  input  wire                              m05_axi_bvalid ,
  output wire                              m05_axi_bready ,
  output wire                              m05_axi_arvalid,
  input  wire                              m05_axi_arready,
  output wire [C_M05_AXI_ADDR_WIDTH-1:0]   m05_axi_araddr ,
  output wire [8-1:0]                      m05_axi_arlen  ,
  input  wire                              m05_axi_rvalid ,
  output wire                              m05_axi_rready ,
  input  wire [C_M05_AXI_DATA_WIDTH-1:0]   m05_axi_rdata  ,
  input  wire                              m05_axi_rlast  ,
  // AXI4 master interface m06_axi
  output wire                              m06_axi_awvalid,
  input  wire                              m06_axi_awready,
  output wire [C_M06_AXI_ADDR_WIDTH-1:0]   m06_axi_awaddr ,
  output wire [8-1:0]                      m06_axi_awlen  ,
  output wire                              m06_axi_wvalid ,
  input  wire                              m06_axi_wready ,
  output wire [C_M06_AXI_DATA_WIDTH-1:0]   m06_axi_wdata  ,
  output wire [C_M06_AXI_DATA_WIDTH/8-1:0] m06_axi_wstrb  ,
  output wire                              m06_axi_wlast  ,
  input  wire                              m06_axi_bvalid ,
  output wire                              m06_axi_bready ,
  output wire                              m06_axi_arvalid,
  input  wire                              m06_axi_arready,
  output wire [C_M06_AXI_ADDR_WIDTH-1:0]   m06_axi_araddr ,
  output wire [8-1:0]                      m06_axi_arlen  ,
  input  wire                              m06_axi_rvalid ,
  output wire                              m06_axi_rready ,
  input  wire [C_M06_AXI_DATA_WIDTH-1:0]   m06_axi_rdata  ,
  input  wire                              m06_axi_rlast  ,
  // AXI4 master interface m07_axi
  output wire                              m07_axi_awvalid,
  input  wire                              m07_axi_awready,
  output wire [C_M07_AXI_ADDR_WIDTH-1:0]   m07_axi_awaddr ,
  output wire [8-1:0]                      m07_axi_awlen  ,
  output wire                              m07_axi_wvalid ,
  input  wire                              m07_axi_wready ,
  output wire [C_M07_AXI_DATA_WIDTH-1:0]   m07_axi_wdata  ,
  output wire [C_M07_AXI_DATA_WIDTH/8-1:0] m07_axi_wstrb  ,
  output wire                              m07_axi_wlast  ,
  input  wire                              m07_axi_bvalid ,
  output wire                              m07_axi_bready ,
  output wire                              m07_axi_arvalid,
  input  wire                              m07_axi_arready,
  output wire [C_M07_AXI_ADDR_WIDTH-1:0]   m07_axi_araddr ,
  output wire [8-1:0]                      m07_axi_arlen  ,
  input  wire                              m07_axi_rvalid ,
  output wire                              m07_axi_rready ,
  input  wire [C_M07_AXI_DATA_WIDTH-1:0]   m07_axi_rdata  ,
  input  wire                              m07_axi_rlast  ,
  // AXI4 master interface m08_axi
  output wire                              m08_axi_awvalid,
  input  wire                              m08_axi_awready,
  output wire [C_M08_AXI_ADDR_WIDTH-1:0]   m08_axi_awaddr ,
  output wire [8-1:0]                      m08_axi_awlen  ,
  output wire                              m08_axi_wvalid ,
  input  wire                              m08_axi_wready ,
  output wire [C_M08_AXI_DATA_WIDTH-1:0]   m08_axi_wdata  ,
  output wire [C_M08_AXI_DATA_WIDTH/8-1:0] m08_axi_wstrb  ,
  output wire                              m08_axi_wlast  ,
  input  wire                              m08_axi_bvalid ,
  output wire                              m08_axi_bready ,
  output wire                              m08_axi_arvalid,
  input  wire                              m08_axi_arready,
  output wire [C_M08_AXI_ADDR_WIDTH-1:0]   m08_axi_araddr ,
  output wire [8-1:0]                      m08_axi_arlen  ,
  input  wire                              m08_axi_rvalid ,
  output wire                              m08_axi_rready ,
  input  wire [C_M08_AXI_DATA_WIDTH-1:0]   m08_axi_rdata  ,
  input  wire                              m08_axi_rlast  ,
  // AXI4 master interface m09_axi
  output wire                              m09_axi_awvalid,
  input  wire                              m09_axi_awready,
  output wire [C_M09_AXI_ADDR_WIDTH-1:0]   m09_axi_awaddr ,
  output wire [8-1:0]                      m09_axi_awlen  ,
  output wire                              m09_axi_wvalid ,
  input  wire                              m09_axi_wready ,
  output wire [C_M09_AXI_DATA_WIDTH-1:0]   m09_axi_wdata  ,
  output wire [C_M09_AXI_DATA_WIDTH/8-1:0] m09_axi_wstrb  ,
  output wire                              m09_axi_wlast  ,
  input  wire                              m09_axi_bvalid ,
  output wire                              m09_axi_bready ,
  output wire                              m09_axi_arvalid,
  input  wire                              m09_axi_arready,
  output wire [C_M09_AXI_ADDR_WIDTH-1:0]   m09_axi_araddr ,
  output wire [8-1:0]                      m09_axi_arlen  ,
  input  wire                              m09_axi_rvalid ,
  output wire                              m09_axi_rready ,
  input  wire [C_M09_AXI_DATA_WIDTH-1:0]   m09_axi_rdata  ,
  input  wire                              m09_axi_rlast  ,
  // AXI4 master interface m10_axi
  output wire                              m10_axi_awvalid,
  input  wire                              m10_axi_awready,
  output wire [C_M10_AXI_ADDR_WIDTH-1:0]   m10_axi_awaddr ,
  output wire [8-1:0]                      m10_axi_awlen  ,
  output wire                              m10_axi_wvalid ,
  input  wire                              m10_axi_wready ,
  output wire [C_M10_AXI_DATA_WIDTH-1:0]   m10_axi_wdata  ,
  output wire [C_M10_AXI_DATA_WIDTH/8-1:0] m10_axi_wstrb  ,
  output wire                              m10_axi_wlast  ,
  input  wire                              m10_axi_bvalid ,
  output wire                              m10_axi_bready ,
  output wire                              m10_axi_arvalid,
  input  wire                              m10_axi_arready,
  output wire [C_M10_AXI_ADDR_WIDTH-1:0]   m10_axi_araddr ,
  output wire [8-1:0]                      m10_axi_arlen  ,
  input  wire                              m10_axi_rvalid ,
  output wire                              m10_axi_rready ,
  input  wire [C_M10_AXI_DATA_WIDTH-1:0]   m10_axi_rdata  ,
  input  wire                              m10_axi_rlast  ,
  // AXI4 master interface m11_axi
  output wire                              m11_axi_awvalid,
  input  wire                              m11_axi_awready,
  output wire [C_M11_AXI_ADDR_WIDTH-1:0]   m11_axi_awaddr ,
  output wire [8-1:0]                      m11_axi_awlen  ,
  output wire                              m11_axi_wvalid ,
  input  wire                              m11_axi_wready ,
  output wire [C_M11_AXI_DATA_WIDTH-1:0]   m11_axi_wdata  ,
  output wire [C_M11_AXI_DATA_WIDTH/8-1:0] m11_axi_wstrb  ,
  output wire                              m11_axi_wlast  ,
  input  wire                              m11_axi_bvalid ,
  output wire                              m11_axi_bready ,
  output wire                              m11_axi_arvalid,
  input  wire                              m11_axi_arready,
  output wire [C_M11_AXI_ADDR_WIDTH-1:0]   m11_axi_araddr ,
  output wire [8-1:0]                      m11_axi_arlen  ,
  input  wire                              m11_axi_rvalid ,
  output wire                              m11_axi_rready ,
  input  wire [C_M11_AXI_DATA_WIDTH-1:0]   m11_axi_rdata  ,
  input  wire                              m11_axi_rlast  ,
  // SDx Control Signals
  input  wire                              ap_start       ,
  output wire                              ap_idle        ,
  output wire                              ap_done        ,
  output wire                              ap_ready       ,
  input  wire [32-1:0]                     iterator_max   ,
  input  wire [32-1:0]                     vertex_num     ,
  input  wire [32-1:0]                     edge_num       ,
  input  wire [64-1:0]                     A_1            ,
  input  wire [64-1:0]                     A_2            ,
  input  wire [64-1:0]                     B_1            ,
  input  wire [64-1:0]                     B_2            ,
  input  wire [64-1:0]                     C              ,
  input  wire [64-1:0]                     D_1            ,
  input  wire [64-1:0]                     D_2            ,
  input  wire [64-1:0]                     D_3            ,
  input  wire [64-1:0]                     D_4            ,
  input  wire [64-1:0]                     E              ,
  input  wire [64-1:0]                     F_1            ,
  input  wire [64-1:0]                     F_2            
);


timeunit 1ps;
timeprecision 1ps;

///////////////////////////////////////////////////////////////////////////////
// Local Parameters
///////////////////////////////////////////////////////////////////////////////
localparam integer  LP_NUM_EXAMPLES    = 12;

///////////////////////////////////////////////////////////////////////////////
// Wires and Variables
///////////////////////////////////////////////////////////////////////////////
(* KEEP = "yes" *)
logic                                areset                         = 1'b0;
logic                                ap_start_r                     = 1'b0;
logic                                ap_start_r_acc                 = 1'b0;
logic                                ap_idle_r                      = 1'b1;
logic                                ap_start_pulse                ;
logic                                ap_start_pulse_acc            ;
logic [LP_NUM_EXAMPLES-1:0]          ap_done_i                     ;
logic [LP_NUM_EXAMPLES-1:0]          ap_done_r                      = {LP_NUM_EXAMPLES{1'b0}};
logic [32-1:0]                       ctrl_constant                  = 32'd1;

// for Accelerator
// read
logic                             rd_tvalid_offset_1, rd_tvalid_offset_2;
logic                             rd_tready_offset_1, rd_tready_offset_2;
logic                             rd_tlast_offset_1, rd_tlast_offset_2;
logic [C_M00_AXI_DATA_WIDTH-1:0]  rd_tdata_offset_1, rd_tdata_offset_2;
logic                             rd_tvalid_info_1, rd_tvalid_info_2;
logic                             rd_tready_info_1, rd_tready_info_2;
logic                             rd_tlast_info_1, rd_tlast_info_2;
logic [C_M02_AXI_DATA_WIDTH-1:0]  rd_tdata_info_1, rd_tdata_info_2;
logic                             rd_tvalid_degree_1, rd_tvalid_degree_2;
logic                             rd_tready_degree_1, rd_tready_degree_2;
logic                             rd_tlast_degree_1, rd_tlast_degree_2;
logic [C_M10_AXI_DATA_WIDTH-1:0]  rd_tdata_degree_1, rd_tdata_degree_2;
// write
// vertex data
logic                             wr_tvalid_vertex_data;
logic                             wr_tready_vertex_data;
logic                             wr_tlast_vertex_data;
logic [C_M04_AXI_DATA_WIDTH-1:0]  wr_tdata_vertex_data;
// vertex id
logic                             wr_tvalid_vertex_id_1;
logic                             wr_tvalid_vertex_id_2;
logic                             wr_tvalid_vertex_id_3;
logic                             wr_tvalid_vertex_id_4;
logic                             wr_tready_vertex_id_1;
logic                             wr_tready_vertex_id_2;
logic                             wr_tready_vertex_id_3;
logic                             wr_tready_vertex_id_4;
logic                             wr_tlast_vertex_id_1;
logic                             wr_tlast_vertex_id_2;
logic                             wr_tlast_vertex_id_3;
logic                             wr_tlast_vertex_id_4;
logic [C_M05_AXI_DATA_WIDTH-1:0]  wr_tdata_vertex_id_1;
logic [C_M05_AXI_DATA_WIDTH-1:0]  wr_tdata_vertex_id_2;
logic [C_M05_AXI_DATA_WIDTH-1:0]  wr_tdata_vertex_id_3;
logic [C_M05_AXI_DATA_WIDTH-1:0]  wr_tdata_vertex_id_4;
// cycle
logic                             wr_tvalid_cycle;
logic                             wr_tready_cycle;
logic                             wr_tlast_cycle;
logic [C_M09_AXI_DATA_WIDTH-1:0]  wr_tdata_cycle;

// from kernel
logic                             acc_start;
logic                             wr_cn_rst;
logic                             rd_cn_rst;
///////////////////////////////////////////////////////////////////////////////
// Begin RTL
///////////////////////////////////////////////////////////////////////////////

// Register and invert reset signal.
always @(posedge ap_clk) begin
  areset <= ~ap_rst_n;
end

// create pulse when ap_start transitions to 1
always @(posedge ap_clk) begin
  begin
    // ap_start_r <= ap_start;
    ap_start_r <= acc_start;
    ap_start_r_acc <= ap_start;
  end
end

// assign ap_start_pulse = ap_start & ~ap_start_r;
assign ap_start_pulse = acc_start & ~ap_start_r; // this signal for read and write channel
assign ap_start_pulse_acc = ap_start & ~ap_start_r_acc;

// ap_idle is asserted when done is asserted, it is de-asserted when ap_start_pulse
// is asserted
always @(posedge ap_clk) begin
  if (areset) begin
    ap_idle_r <= 1'b1;
  end
  else begin
    ap_idle_r <= ap_done ? 1'b1 :
      ap_start_pulse ? 1'b0 : ap_idle;
  end
end

assign ap_idle = ap_idle_r;

// Done logic
always @(posedge ap_clk) begin
  if (areset) begin
    ap_done_r <= '0;
  end
  else begin
    ap_done_r <= (ap_start_pulse | ap_done) ? '0 : ap_done_r | ap_done_i;
  end
end

assign ap_done = &ap_done_r;
assign ap_ready = ap_done;

wire kernel_clk, kernel_rst;
assign kernel_clk = ap_clk;
assign kernel_rst = areset;

// Accelerator offset_1 read
Accelerator_Indata #(
  .C_M_AXI_ADDR_WIDTH ( C_M00_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M00_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Indata_Offset_1 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( rd_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .iterator_max            ( iterator_max            ),
  .ctrl_addr_offset        ( A_1                     ),
  .ctrl_xfer_size_in_bytes ( ((((vertex_num + 1) >> 1) & 32'hfffffff0) + (((vertex_num + 1) & 32'h0000001f) > 0 ? 16 : 0)) << 2 ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[0]            ),
  .m_axi_awvalid           ( m00_axi_awvalid         ),
  .m_axi_awready           ( m00_axi_awready         ),
  .m_axi_awaddr            ( m00_axi_awaddr          ),
  .m_axi_awlen             ( m00_axi_awlen           ),
  .m_axi_wvalid            ( m00_axi_wvalid          ),
  .m_axi_wready            ( m00_axi_wready          ),
  .m_axi_wdata             ( m00_axi_wdata           ),
  .m_axi_wstrb             ( m00_axi_wstrb           ),
  .m_axi_wlast             ( m00_axi_wlast           ),
  .m_axi_bvalid            ( m00_axi_bvalid          ),
  .m_axi_bready            ( m00_axi_bready          ),
  .m_axi_arvalid           ( m00_axi_arvalid         ),
  .m_axi_arready           ( m00_axi_arready         ),
  .m_axi_araddr            ( m00_axi_araddr          ),
  .m_axi_arlen             ( m00_axi_arlen           ),
  .m_axi_rvalid            ( m00_axi_rvalid          ),
  .m_axi_rready            ( m00_axi_rready          ),
  .m_axi_rdata             ( m00_axi_rdata           ),
  .m_axi_rlast             ( m00_axi_rlast           ),
  .rd_tvalid               ( rd_tvalid_offset_1      ),
  .rd_tready               ( rd_tready_offset_1      ), // 控制fifo read
  .rd_tlast                ( rd_tlast_offset_1       ),
  .rd_tdata                ( rd_tdata_offset_1       )
);
// offset 2
Accelerator_Indata #(
  .C_M_AXI_ADDR_WIDTH ( C_M01_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M01_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Indata_Offset_2 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( rd_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .iterator_max            ( iterator_max            ),
  .ctrl_addr_offset        ( A_2                     ),
  .ctrl_xfer_size_in_bytes ( ((((vertex_num + 1) >> 1) & 32'hfffffff0) + (((vertex_num + 1) & 32'h0000001f) > 0 ? 16 : 0)) << 2 ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[1]            ),
  .m_axi_awvalid           ( m01_axi_awvalid         ),
  .m_axi_awready           ( m01_axi_awready         ),
  .m_axi_awaddr            ( m01_axi_awaddr          ),
  .m_axi_awlen             ( m01_axi_awlen           ),
  .m_axi_wvalid            ( m01_axi_wvalid          ),
  .m_axi_wready            ( m01_axi_wready          ),
  .m_axi_wdata             ( m01_axi_wdata           ),
  .m_axi_wstrb             ( m01_axi_wstrb           ),
  .m_axi_wlast             ( m01_axi_wlast           ),
  .m_axi_bvalid            ( m01_axi_bvalid          ),
  .m_axi_bready            ( m01_axi_bready          ),
  .m_axi_arvalid           ( m01_axi_arvalid         ),
  .m_axi_arready           ( m01_axi_arready         ),
  .m_axi_araddr            ( m01_axi_araddr          ),
  .m_axi_arlen             ( m01_axi_arlen           ),
  .m_axi_rvalid            ( m01_axi_rvalid          ),
  .m_axi_rready            ( m01_axi_rready          ),
  .m_axi_rdata             ( m01_axi_rdata           ),
  .m_axi_rlast             ( m01_axi_rlast           ),
  .rd_tvalid               ( rd_tvalid_offset_2      ),
  .rd_tready               ( rd_tready_offset_2      ), // 控制fifo read
  .rd_tlast                ( rd_tlast_offset_2       ),
  .rd_tdata                ( rd_tdata_offset_2       )
);
// Accelerator info 1 read
Accelerator_Indata #(
  .C_M_AXI_ADDR_WIDTH ( C_M02_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M02_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Indata_Info_1 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( rd_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .iterator_max            ( iterator_max            ),
  .ctrl_addr_offset        ( B_1                     ),
  .ctrl_xfer_size_in_bytes ( ((((edge_num + 1) >> 1) & 32'hfffffff0) + (((edge_num + 1) & 32'h0000001f) > 0 ? 16 : 0)) << 2 ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[2]            ),
  .m_axi_awvalid           ( m02_axi_awvalid         ),
  .m_axi_awready           ( m02_axi_awready         ),
  .m_axi_awaddr            ( m02_axi_awaddr          ),
  .m_axi_awlen             ( m02_axi_awlen           ),
  .m_axi_wvalid            ( m02_axi_wvalid          ),
  .m_axi_wready            ( m02_axi_wready          ),
  .m_axi_wdata             ( m02_axi_wdata           ),
  .m_axi_wstrb             ( m02_axi_wstrb           ),
  .m_axi_wlast             ( m02_axi_wlast           ),
  .m_axi_bvalid            ( m02_axi_bvalid          ),
  .m_axi_bready            ( m02_axi_bready          ),
  .m_axi_arvalid           ( m02_axi_arvalid         ),
  .m_axi_arready           ( m02_axi_arready         ),
  .m_axi_araddr            ( m02_axi_araddr          ),
  .m_axi_arlen             ( m02_axi_arlen           ),
  .m_axi_rvalid            ( m02_axi_rvalid          ),
  .m_axi_rready            ( m02_axi_rready          ),
  .m_axi_rdata             ( m02_axi_rdata           ),
  .m_axi_rlast             ( m02_axi_rlast           ),
  .rd_tvalid             ( rd_tvalid_info_1          ),
  .rd_tready             ( rd_tready_info_1          ), // 控制fifo read
  .rd_tlast              ( rd_tlast_info_1           ),
  .rd_tdata              ( rd_tdata_info_1           )
);
// Accelerator info 2 read
Accelerator_Indata #(
  .C_M_AXI_ADDR_WIDTH ( C_M03_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M03_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Indata_Info_2 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( rd_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .iterator_max            ( iterator_max            ),
  .ctrl_addr_offset        ( B_2                     ),
  .ctrl_xfer_size_in_bytes ( ((((edge_num + 1) >> 1) & 32'hfffffff0) + (((edge_num + 1) & 32'h0000001f) > 0 ? 16 : 0)) << 2 ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[3]            ),
  .m_axi_awvalid           ( m03_axi_awvalid         ),
  .m_axi_awready           ( m03_axi_awready         ),
  .m_axi_awaddr            ( m03_axi_awaddr          ),
  .m_axi_awlen             ( m03_axi_awlen           ),
  .m_axi_wvalid            ( m03_axi_wvalid          ),
  .m_axi_wready            ( m03_axi_wready          ),
  .m_axi_wdata             ( m03_axi_wdata           ),
  .m_axi_wstrb             ( m03_axi_wstrb           ),
  .m_axi_wlast             ( m03_axi_wlast           ),
  .m_axi_bvalid            ( m03_axi_bvalid          ),
  .m_axi_bready            ( m03_axi_bready          ),
  .m_axi_arvalid           ( m03_axi_arvalid         ),
  .m_axi_arready           ( m03_axi_arready         ),
  .m_axi_araddr            ( m03_axi_araddr          ),
  .m_axi_arlen             ( m03_axi_arlen           ),
  .m_axi_rvalid            ( m03_axi_rvalid          ),
  .m_axi_rready            ( m03_axi_rready          ),
  .m_axi_rdata             ( m03_axi_rdata           ),
  .m_axi_rlast             ( m03_axi_rlast           ),
  .rd_tvalid             ( rd_tvalid_info_2          ),
  .rd_tready             ( rd_tready_info_2          ), // 控制fifo read
  .rd_tlast              ( rd_tlast_info_2           ),
  .rd_tdata              ( rd_tdata_info_2           )
);

// Accelerator logic
Accelerator_Top #(
  .OFFSET_CHANNEL_WIDTH     (C_M00_AXI_DATA_WIDTH),
  .INFO_CHANNEL_WIDTH       (C_M02_AXI_DATA_WIDTH),
  .VERTEX_DATA_CHANNEL_WIDTH(C_M04_AXI_DATA_WIDTH),
  .VERTEX_ID_CHANNEL_WIDTH  (C_M05_AXI_DATA_WIDTH),
  .CYCLE_CHANNEL_WIDTH      (C_M09_AXI_DATA_WIDTH)
)
Accelerator_Top (
  .kernel_clk                (kernel_clk),
  .kernel_rst                (kernel_rst),
  .ctrl_constant             (ctrl_constant),
  .ctrl_start                (ap_start_pulse_acc), // 专用启动信号
  .iterator_max              (iterator_max),
  .vertex_num                (vertex_num),
  .edge_num                  (edge_num),
  .wr_done                   (1'b0),  // TODO : not use of this signal

  .s_Offset_axis_tvalid_1    (rd_tvalid_offset_1),
  .s_Offset_axis_tready_1    (rd_tready_offset_1),
  .s_Offset_axis_tdata_1     (rd_tdata_offset_1),
  .s_Offset_axis_tlast_1     (rd_tlast_offset_1),

  .s_Offset_axis_tvalid_2    (rd_tvalid_offset_2),
  .s_Offset_axis_tready_2    (rd_tready_offset_2),
  .s_Offset_axis_tdata_2     (rd_tdata_offset_2),
  .s_Offset_axis_tlast_2     (rd_tlast_offset_2),

  .s_Info_axis_tvalid_1      (rd_tvalid_info_1),
  .s_Info_axis_tready_1      (rd_tready_info_1),
  .s_Info_axis_tdata_1       (rd_tdata_info_1),
  .s_Info_axis_tlast_1       (rd_tlast_info_1),

  .s_Info_axis_tvalid_2      (rd_tvalid_info_2),
  .s_Info_axis_tready_2      (rd_tready_info_2),
  .s_Info_axis_tdata_2       (rd_tdata_info_2),
  .s_Info_axis_tlast_2       (rd_tlast_info_2),

  .s_Degree_axis_tvalid_1      (rd_tvalid_degree_1),
  .s_Degree_axis_tready_1      (rd_tready_degree_1),
  .s_Degree_axis_tdata_1       (rd_tdata_degree_1),
  .s_Degree_axis_tlast_1       (rd_tlast_degree_1),

  .s_Degree_axis_tvalid_2      (rd_tvalid_degree_2),
  .s_Degree_axis_tready_2      (rd_tready_degree_2),
  .s_Degree_axis_tdata_2       (rd_tdata_degree_2),
  .s_Degree_axis_tlast_2       (rd_tlast_degree_2),

  .m_Vertex_Data_axis_aclk   (kernel_clk),
  .m_Vertex_Data_axis_tvalid (wr_tvalid_vertex_data),
  .m_Vertex_Data_axis_tready (wr_tready_vertex_data),
  .m_Vertex_Data_axis_tdata  (wr_tdata_vertex_data),
  .m_Vertex_Data_axis_tlast  (wr_tlast_vertex_data),

  .m_Vertex_Id_axis_aclk_1   (kernel_clk),
  .m_Vertex_Id_axis_tvalid_1 (wr_tvalid_vertex_id_1),
  .m_Vertex_Id_axis_tready_1 (wr_tready_vertex_id_1),
  .m_Vertex_Id_axis_tdata_1  (wr_tdata_vertex_id_1),
  .m_Vertex_Id_axis_tlast_1  (wr_tlast_vertex_id_1),

  .m_Vertex_Id_axis_aclk_2   (kernel_clk),
  .m_Vertex_Id_axis_tvalid_2 (wr_tvalid_vertex_id_2),
  .m_Vertex_Id_axis_tready_2 (wr_tready_vertex_id_2),
  .m_Vertex_Id_axis_tdata_2  (wr_tdata_vertex_id_2),
  .m_Vertex_Id_axis_tlast_2  (wr_tlast_vertex_id_2),

  .m_Vertex_Id_axis_aclk_3   (kernel_clk),
  .m_Vertex_Id_axis_tvalid_3 (wr_tvalid_vertex_id_3),
  .m_Vertex_Id_axis_tready_3 (wr_tready_vertex_id_3),
  .m_Vertex_Id_axis_tdata_3  (wr_tdata_vertex_id_3),
  .m_Vertex_Id_axis_tlast_3  (wr_tlast_vertex_id_3),

  .m_Vertex_Id_axis_aclk_4   (kernel_clk),
  .m_Vertex_Id_axis_tvalid_4 (wr_tvalid_vertex_id_4),
  .m_Vertex_Id_axis_tready_4 (wr_tready_vertex_id_4),
  .m_Vertex_Id_axis_tdata_4  (wr_tdata_vertex_id_4),
  .m_Vertex_Id_axis_tlast_4  (wr_tlast_vertex_id_4),

  .m_Cycle_axis_aclk         (kernel_clk),
  .m_Cycle_axis_tvalid       (wr_tvalid_cycle),
  .m_Cycle_axis_tready       (wr_tready_cycle),
  .m_Cycle_axis_tdata        (wr_tdata_cycle),
  .m_Cycle_axis_tlast        (wr_tlast_cycle),
  
  .acc_start                 (acc_start),
  .rd_cn_rst                 (rd_cn_rst),
  .wr_cn_rst                 (wr_cn_rst));

// Accelerator vertex data write
Accelerator_Outdata #(
  .C_M_AXI_ADDR_WIDTH ( C_M04_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M04_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Outdata_Vertex_Data (
  .aclk                    ( ap_clk                  ),
  .areset                  ( wr_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .ctrl_addr_offset        ( C                       ),
  .ctrl_xfer_size_in_bytes ( (vertex_num + 64) * 2   ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[4]            ),
  .m_axi_awvalid           ( m04_axi_awvalid         ),
  .m_axi_awready           ( m04_axi_awready         ),
  .m_axi_awaddr            ( m04_axi_awaddr          ),
  .m_axi_awlen             ( m04_axi_awlen           ),
  .m_axi_wvalid            ( m04_axi_wvalid          ),
  .m_axi_wready            ( m04_axi_wready          ),
  .m_axi_wdata             ( m04_axi_wdata           ),
  .m_axi_wstrb             ( m04_axi_wstrb           ),
  .m_axi_wlast             ( m04_axi_wlast           ),
  .m_axi_bvalid            ( m04_axi_bvalid          ),
  .m_axi_bready            ( m04_axi_bready          ),
  .m_axi_arvalid           ( m04_axi_arvalid         ),
  .m_axi_arready           ( m04_axi_arready         ),
  .m_axi_araddr            ( m04_axi_araddr          ),
  .m_axi_arlen             ( m04_axi_arlen           ),
  .m_axi_rvalid            ( m04_axi_rvalid          ),
  .m_axi_rready            ( m04_axi_rready          ),
  .m_axi_rdata             ( m04_axi_rdata           ),
  .m_axi_rlast             ( m04_axi_rlast           ),
  .a_rd_tvalid             ( wr_tvalid_vertex_data   ),
  .a_rd_tready             ( wr_tready_vertex_data   ), // 控制fifo write
  .a_rd_tlast              ( wr_tlast_vertex_data    ),
  .a_rd_tdata              ( wr_tdata_vertex_data    )
);

// Accelerator vertex id 1 write
Accelerator_Outdata #(
  .C_M_AXI_ADDR_WIDTH ( C_M05_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M05_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Outdata_Vertex_id_1 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( wr_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .ctrl_addr_offset        ( D_1                     ),
  .ctrl_xfer_size_in_bytes ( vertex_num + 64         ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[5]            ),
  .m_axi_awvalid           ( m05_axi_awvalid         ),
  .m_axi_awready           ( m05_axi_awready         ),
  .m_axi_awaddr            ( m05_axi_awaddr          ),
  .m_axi_awlen             ( m05_axi_awlen           ),
  .m_axi_wvalid            ( m05_axi_wvalid          ),
  .m_axi_wready            ( m05_axi_wready          ),
  .m_axi_wdata             ( m05_axi_wdata           ),
  .m_axi_wstrb             ( m05_axi_wstrb           ),
  .m_axi_wlast             ( m05_axi_wlast           ),
  .m_axi_bvalid            ( m05_axi_bvalid          ),
  .m_axi_bready            ( m05_axi_bready          ),
  .m_axi_arvalid           ( m05_axi_arvalid         ),
  .m_axi_arready           ( m05_axi_arready         ),
  .m_axi_araddr            ( m05_axi_araddr          ),
  .m_axi_arlen             ( m05_axi_arlen           ),
  .m_axi_rvalid            ( m05_axi_rvalid          ),
  .m_axi_rready            ( m05_axi_rready          ),
  .m_axi_rdata             ( m05_axi_rdata           ),
  .m_axi_rlast             ( m05_axi_rlast           ),
  .a_rd_tvalid             ( wr_tvalid_vertex_id_1   ),
  .a_rd_tready             ( wr_tready_vertex_id_1   ), // 控制fifo write
  .a_rd_tlast              ( wr_tlast_vertex_id_1    ),
  .a_rd_tdata              ( wr_tdata_vertex_id_1    )
);

// Accelerator vertex id 2 write
Accelerator_Outdata #(
  .C_M_AXI_ADDR_WIDTH ( C_M06_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M06_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Outdata_Vertex_id_2 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( wr_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .ctrl_addr_offset        ( D_2                     ),
  .ctrl_xfer_size_in_bytes ( vertex_num + 64         ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[6]            ),
  .m_axi_awvalid           ( m06_axi_awvalid         ),
  .m_axi_awready           ( m06_axi_awready         ),
  .m_axi_awaddr            ( m06_axi_awaddr          ),
  .m_axi_awlen             ( m06_axi_awlen           ),
  .m_axi_wvalid            ( m06_axi_wvalid          ),
  .m_axi_wready            ( m06_axi_wready          ),
  .m_axi_wdata             ( m06_axi_wdata           ),
  .m_axi_wstrb             ( m06_axi_wstrb           ),
  .m_axi_wlast             ( m06_axi_wlast           ),
  .m_axi_bvalid            ( m06_axi_bvalid          ),
  .m_axi_bready            ( m06_axi_bready          ),
  .m_axi_arvalid           ( m06_axi_arvalid         ),
  .m_axi_arready           ( m06_axi_arready         ),
  .m_axi_araddr            ( m06_axi_araddr          ),
  .m_axi_arlen             ( m06_axi_arlen           ),
  .m_axi_rvalid            ( m06_axi_rvalid          ),
  .m_axi_rready            ( m06_axi_rready          ),
  .m_axi_rdata             ( m06_axi_rdata           ),
  .m_axi_rlast             ( m06_axi_rlast           ),
  .a_rd_tvalid             ( wr_tvalid_vertex_id_2   ),
  .a_rd_tready             ( wr_tready_vertex_id_2   ), // 控制fifo write
  .a_rd_tlast              ( wr_tlast_vertex_id_2    ),
  .a_rd_tdata              ( wr_tdata_vertex_id_2    )
);

// Accelerator vertex id 3 write
Accelerator_Outdata #(
  .C_M_AXI_ADDR_WIDTH ( C_M07_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M07_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Outdata_Vertex_id_3 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( wr_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .ctrl_addr_offset        ( D_3                     ),
  .ctrl_xfer_size_in_bytes ( vertex_num + 64         ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[7]            ),
  .m_axi_awvalid           ( m07_axi_awvalid         ),
  .m_axi_awready           ( m07_axi_awready         ),
  .m_axi_awaddr            ( m07_axi_awaddr          ),
  .m_axi_awlen             ( m07_axi_awlen           ),
  .m_axi_wvalid            ( m07_axi_wvalid          ),
  .m_axi_wready            ( m07_axi_wready          ),
  .m_axi_wdata             ( m07_axi_wdata           ),
  .m_axi_wstrb             ( m07_axi_wstrb           ),
  .m_axi_wlast             ( m07_axi_wlast           ),
  .m_axi_bvalid            ( m07_axi_bvalid          ),
  .m_axi_bready            ( m07_axi_bready          ),
  .m_axi_arvalid           ( m07_axi_arvalid         ),
  .m_axi_arready           ( m07_axi_arready         ),
  .m_axi_araddr            ( m07_axi_araddr          ),
  .m_axi_arlen             ( m07_axi_arlen           ),
  .m_axi_rvalid            ( m07_axi_rvalid          ),
  .m_axi_rready            ( m07_axi_rready          ),
  .m_axi_rdata             ( m07_axi_rdata           ),
  .m_axi_rlast             ( m07_axi_rlast           ),
  .a_rd_tvalid             ( wr_tvalid_vertex_id_3   ),
  .a_rd_tready             ( wr_tready_vertex_id_3   ), // 控制fifo write
  .a_rd_tlast              ( wr_tlast_vertex_id_3    ),
  .a_rd_tdata              ( wr_tdata_vertex_id_3    )
);

// Accelerator vertex id 4 write
Accelerator_Outdata #(
  .C_M_AXI_ADDR_WIDTH ( C_M08_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M08_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Outdata_Vertex_id_4 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( wr_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .ctrl_addr_offset        ( D_4                     ),
  .ctrl_xfer_size_in_bytes ( vertex_num + 64         ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[8]            ),
  .m_axi_awvalid           ( m08_axi_awvalid         ),
  .m_axi_awready           ( m08_axi_awready         ),
  .m_axi_awaddr            ( m08_axi_awaddr          ),
  .m_axi_awlen             ( m08_axi_awlen           ),
  .m_axi_wvalid            ( m08_axi_wvalid          ),
  .m_axi_wready            ( m08_axi_wready          ),
  .m_axi_wdata             ( m08_axi_wdata           ),
  .m_axi_wstrb             ( m08_axi_wstrb           ),
  .m_axi_wlast             ( m08_axi_wlast           ),
  .m_axi_bvalid            ( m08_axi_bvalid          ),
  .m_axi_bready            ( m08_axi_bready          ),
  .m_axi_arvalid           ( m08_axi_arvalid         ),
  .m_axi_arready           ( m08_axi_arready         ),
  .m_axi_araddr            ( m08_axi_araddr          ),
  .m_axi_arlen             ( m08_axi_arlen           ),
  .m_axi_rvalid            ( m08_axi_rvalid          ),
  .m_axi_rready            ( m08_axi_rready          ),
  .m_axi_rdata             ( m08_axi_rdata           ),
  .m_axi_rlast             ( m08_axi_rlast           ),
  .a_rd_tvalid             ( wr_tvalid_vertex_id_4   ),
  .a_rd_tready             ( wr_tready_vertex_id_4   ), // 控制fifo write
  .a_rd_tlast              ( wr_tlast_vertex_id_4    ),
  .a_rd_tdata              ( wr_tdata_vertex_id_4    )
);

// Accelerator cycle write
Accelerator_Outdata #(
  .C_M_AXI_ADDR_WIDTH ( C_M09_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M09_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Outdata_Cycle (
  .aclk                    ( ap_clk                  ),
  .areset                  ( wr_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .ctrl_addr_offset        ( E ),
  .ctrl_xfer_size_in_bytes ( 4 ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[9]            ),
  .m_axi_awvalid           ( m09_axi_awvalid         ),
  .m_axi_awready           ( m09_axi_awready         ),
  .m_axi_awaddr            ( m09_axi_awaddr          ),
  .m_axi_awlen             ( m09_axi_awlen           ),
  .m_axi_wvalid            ( m09_axi_wvalid          ),
  .m_axi_wready            ( m09_axi_wready          ),
  .m_axi_wdata             ( m09_axi_wdata           ),
  .m_axi_wstrb             ( m09_axi_wstrb           ),
  .m_axi_wlast             ( m09_axi_wlast           ),
  .m_axi_bvalid            ( m09_axi_bvalid          ),
  .m_axi_bready            ( m09_axi_bready          ),
  .m_axi_arvalid           ( m09_axi_arvalid         ),
  .m_axi_arready           ( m09_axi_arready         ),
  .m_axi_araddr            ( m09_axi_araddr          ),
  .m_axi_arlen             ( m09_axi_arlen           ),
  .m_axi_rvalid            ( m09_axi_rvalid          ),
  .m_axi_rready            ( m09_axi_rready          ),
  .m_axi_rdata             ( m09_axi_rdata           ),
  .m_axi_rlast             ( m09_axi_rlast           ),
  .a_rd_tvalid             ( wr_tvalid_cycle         ),
  .a_rd_tready             ( wr_tready_cycle         ), // 控制fifo write
  .a_rd_tlast              ( wr_tlast_cycle          ),
  .a_rd_tdata              ( wr_tdata_cycle          )
);

// Accelerator degree 1 read
Accelerator_Indata #(
  .C_M_AXI_ADDR_WIDTH ( C_M10_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M10_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Indata_Degree_1 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( rd_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .iterator_max            ( iterator_max            ),
  .ctrl_addr_offset        ( F_1                     ),
  .ctrl_xfer_size_in_bytes ( ((((edge_num + 1) >> 1) & 32'hfffffff0) + (((edge_num + 1) & 32'h0000001f) > 0 ? 16 : 0)) << 2 ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[10]            ),
  .m_axi_awvalid           ( m10_axi_awvalid         ),
  .m_axi_awready           ( m10_axi_awready         ),
  .m_axi_awaddr            ( m10_axi_awaddr          ),
  .m_axi_awlen             ( m10_axi_awlen           ),
  .m_axi_wvalid            ( m10_axi_wvalid          ),
  .m_axi_wready            ( m10_axi_wready          ),
  .m_axi_wdata             ( m10_axi_wdata           ),
  .m_axi_wstrb             ( m10_axi_wstrb           ),
  .m_axi_wlast             ( m10_axi_wlast           ),
  .m_axi_bvalid            ( m10_axi_bvalid          ),
  .m_axi_bready            ( m10_axi_bready          ),
  .m_axi_arvalid           ( m10_axi_arvalid         ),
  .m_axi_arready           ( m10_axi_arready         ),
  .m_axi_araddr            ( m10_axi_araddr          ),
  .m_axi_arlen             ( m10_axi_arlen           ),
  .m_axi_rvalid            ( m10_axi_rvalid          ),
  .m_axi_rready            ( m10_axi_rready          ),
  .m_axi_rdata             ( m10_axi_rdata           ),
  .m_axi_rlast             ( m10_axi_rlast           ),
  .rd_tvalid             ( rd_tvalid_degree_1          ),
  .rd_tready             ( rd_tready_degree_1), // 控制fifo read
  .rd_tlast              ( rd_tlast_degree_1),
  .rd_tdata              ( rd_tdata_degree_1)
);
// Accelerator degree 2 read
Accelerator_Indata #(
  .C_M_AXI_ADDR_WIDTH ( C_M11_AXI_ADDR_WIDTH ),
  .C_M_AXI_DATA_WIDTH ( C_M11_AXI_DATA_WIDTH ),
  .C_ADDER_BIT_WIDTH  ( 32                   ),
  .C_XFER_SIZE_WIDTH  ( 32                   )
)
Indata_Degree_2 (
  .aclk                    ( ap_clk                  ),
  .areset                  ( rd_cn_rst               ),
  .kernel_clk              ( kernel_clk              ),
  .kernel_rst              ( kernel_rst              ),
  .iterator_max            ( iterator_max            ),
  .ctrl_addr_offset        ( F_2                     ),
  .ctrl_xfer_size_in_bytes ( ((((edge_num + 1) >> 1) & 32'hfffffff0) + (((edge_num + 1) & 32'h0000001f) > 0 ? 16 : 0)) << 2 ),
  .ctrl_constant           ( ctrl_constant           ),
  .ap_start                ( ap_start_pulse          ),
  .ap_done                 ( ap_done_i[11]            ),
  .m_axi_awvalid           ( m11_axi_awvalid         ),
  .m_axi_awready           ( m11_axi_awready         ),
  .m_axi_awaddr            ( m11_axi_awaddr          ),
  .m_axi_awlen             ( m11_axi_awlen           ),
  .m_axi_wvalid            ( m11_axi_wvalid          ),
  .m_axi_wready            ( m11_axi_wready          ),
  .m_axi_wdata             ( m11_axi_wdata           ),
  .m_axi_wstrb             ( m11_axi_wstrb           ),
  .m_axi_wlast             ( m11_axi_wlast           ),
  .m_axi_bvalid            ( m11_axi_bvalid          ),
  .m_axi_bready            ( m11_axi_bready          ),
  .m_axi_arvalid           ( m11_axi_arvalid         ),
  .m_axi_arready           ( m11_axi_arready         ),
  .m_axi_araddr            ( m11_axi_araddr          ),
  .m_axi_arlen             ( m11_axi_arlen           ),
  .m_axi_rvalid            ( m11_axi_rvalid          ),
  .m_axi_rready            ( m11_axi_rready          ),
  .m_axi_rdata             ( m11_axi_rdata           ),
  .m_axi_rlast             ( m11_axi_rlast           ),
  .rd_tvalid             ( rd_tvalid_degree_2          ),
  .rd_tready             ( rd_tready_degree_2), // 控制fifo read
  .rd_tlast              ( rd_tlast_degree_2),
  .rd_tdata              ( rd_tdata_degree_2)
);
endmodule : Accelerator_top_wrapper
`default_nettype wire